In many applications, such as in temperature measurement using thermocouples, an analog signal must be converted to a corresponding digital signal for data processing or display. Dual-slope integration type analog-to-digital converters are commonly preferred because the conversion accuracy and resolution as well as differential linearity inherent in them are excellent. Furthermore, dual-slope converters exhibit high normal-mode noise rejection and have relatively low long term drift. Dual-slope converters as well as numerous other analog-to-digital conversion techniques are described in Chapter 5 of Hnatek, Eugene, "A Users Handbook of D/A and A/D Converters", John Wiley & Sons, Inc., 1976.
In dual-slope conversion, an unknown input signal is first integrated for a fixed period of time, and the reference signal of a polarity opposite that of the input signal. The length of time required for the integrator to return to zero is proportional to the average magnitude of the input signal over the integration period. Referring to FIG. 1, for example, a two-channel analog-to-digital converter 10 for sampling alternately two different input voltages V.sub.in.sbsb.1 and V.sub.in.sbsb.2 comprises an integrator 12 that receives an input voltage V.sub.in.sbsb.1 or V.sub.in.sbsb.2 through a switch 14 and an amplifier 16. The switch 14, which preferably is formed of solid state switching circuitry controlled by a control unit 18, has its inputs connected to the two input voltage sources V.sub.in.sbsb.1, V.sub.in.sbsb.2 and to a reference voltage source V.sub.ref 20. The polarity of V.sub.ref 20 is opposite that of whichever one of input voltage V.sub.in.sbsb.1 or V.sub.in.sbsb.2 is being measured.
The output of integrator 12 is applied to a comparator 22 which compares the magnitude of the integrated input voltage with ground or with some other reference level that is intermediate the magnitude of the input voltage V.sub.in.sbsb.1, V.sub.in.sbsb.2 being measured and the reference voltage V.sub.ref. A constant rate clock within control unit 18 establishes a timing base for controlling the operation of integrator 12.
The operation of the conventional dual-slope analog-to-digital converter is described with reference to FIG. 2 showing a dual-slope conversion cycle consisting of three regions, Auto-Zero, Integrate and De-Integrate, respectively. During Auto-Zero, errors in analog components of the converter are nulled by storing error information on an "Auto-Zero" capacitor (not shown in FIG. 1). During Integrate, the input voltage V.sub.in.sbsb.1 or V.sub.in.sbsb.2 being measured by switch 14 is integrated by 12 for a fixed time period T.sub.1 determined by control unit 18. During De-Integrate, with switch 14 connected to V.sub.ref 20, the integrated input voltage is de-integrated by 12 toward V.sub.ref. The time T.sub.2 required for output of integrator 12 to intersect ground potential is applied to a counter (not shown) which drives a digital display or is applied to a microcomputer or other circuitry for further processing.
The conversion cycle illustrated in the graph of FIG. 2 corresponds to a single input voltage measurement, that is, measurement of either V.sub.in.sbsb.1 or V.sub.in.sbsb.2 in FIG. 1. The graph of FIG. 3, however, shows two successive conversion cycles wherein switch 14 is first connected to V.sub.in.sbsb.1 to integrate for the fixed time T.sub.1 followed by de-integration toward V.sub.ref and then is connected to a smaller input signal V.sub.in.sbsb.2 to integrate for the time T.sub.1 followed again by de-integration toward V.sub.ref. The de-integration times T.sub.2 associated with the V.sub.in.sbsb.1 and V.sub.in.sbsb.2 measurements are proportional to the magnitudes of the two input voltages, respectively.
Ideally, the two conversions corresponding to input signals V.sub.in.sbsb.1 and V.sub.in.sbsb.2 are mutually independent. As a practical matter, however, if amplifier 16 (FIG. 1) has a metal-oxide-silicon (MOS) input stage, as is commonly the case, they are not. This phenomenon depicted in FIG. 3 by a distortion in the V.sub.2 cycle waveform compared to the ideal waveform (dotted lines) is believed to be caused by ionic migration within the input gate isolation layer 24 (FIG. 4) of the amplifier 14.
The structure and operation of MOS devices as well as of operational amplifiers employing such devices being well known are not described in detail herein. In general, however, the input stage devices of the amplifier 16 comprises a silicon substrate 26 having source 28 and drain 30 diffusions on opposite sides of and beneath gate 32. A gate metallization layer 32 on the upper surface of isolation layer 24, itself formed of silicon dioxide, receives an external control voltage that establishes within the substrate 26 a channel region which controls current flow through the substrate between the drain and source. The mechanisms that take place within isolation layer 24 as sodium ions therein drift in response to an applied gate voltage and change the threshold of the input stage devices of the amplifier 16, and correspondingly alter the offset of the converter 10 are not well known. We believe, however, that the distortion shown in an exaggerated form in FIG. 3 arises as a result of a tendency of free ions in the oxide layer to "stick" in positions established by the input voltage applied during the most recent conversion cycle. The waveform distortion appears to be a function of the magnitude and duration of the signal previously applied to be measured, similar to the capacitive effect known as dielectric absorption. In any case, the de-integration period shown in a solid line in FIG. 3 to be measured to determine input voltage magnitude is somewhat greater than that which would have occured in the absence of the distortion (see the dotted lines in the Figure) inducing in the measurement an error corresponding to .DELTA.T.
An object of this invention, therefore, is to improve isolation by reducing interdependence between successive measurements in an integrating type analog-to-digital converter.
Another object is to provide improved isolation between successive measurements in an integrating analog-to-digital converter of a type having an MOS input stage that has a tendency to retain a conversion residue between successive input signal measurements.
An additional object is to reduce measurement crosstalk between successive measurements in MOS type integrating analog-to-digital converters.